Flash electrically erasable and programmable read-only memories (EEPROM's) are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. FIG. 1 is a cross-sectional view of a conventional flash EEPROM memory cell. The cell 10 is formed on a substrate 12, having a heavily doped drain region 14 and source region 16 embedded therein. The drain and source regions typically contain lightly doped deeply diffused regions 18, 20, respectively, and more heavily doped shallow diffused regions 22, 24, respectively, embedded into the substrate 12. A channel region 26 separates the drain region 14 and source region 16. The cell 10 typically is characterized by a vertical gate stack 36 of a tunnel oxide layer 28, a floating gate 30 over the tunnel oxide layer, an interlevel dielectric layer 32, and a control gate 34 over the interlevel dielectric layer. However, flash memory devices may have other gate stack configurations, such as dual-bit gate stacks, that also are known in the art.
During IC fabrication, a conductive contact 50 is made to the control gate 34, source region 16, and/or the drain region 14 to access the memory device and allow interconnections between the memory device and other devices of the IC, as illustrated in FIG. 2. A conductive contact 50 is an opening through one or more insulating layers 40 that is subsequently filled with a conductive material to form a contact to a device region. The conductive material forming the contact, which often takes the form of a plug, may be tungsten or other metals. However, as the size of integrated circuit devices decreases, fabrication of the contacts to a memory device within the tolerances allowed by the relevant design rules becomes more difficult and has resulted in complex integration schemes for patterning, etching and filling to form the contacts. Misaligned contacts, such as contact 52, pose a significant challenge and can severely reduce device yield.
Accordingly, it is desirable to provide an improved method for forming a contact to a memory device that reduces complex overlay and masking steps. In addition, it is desirable to provide a method for forming a contact to a memory device that facilitates increased device density. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.